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msc5301b-02 ? semiconductor 1/15 general description the msc5301b-02 is an lcd driver lsi with a built-in ram. the device's bit mapping method offers greater flexibility in which each bit of the display ram controls each section on the lcd panel. it can form a graphic display system of 64 x 8 dots in one chip. in addition, the display can be expanded by using the additional lsis. features ? lcd driving voltage range : 6 to 16v ? operating power supply voltage range : 5v 10% ? display duty : 1/8 (1/4 bias) ? common output : 8 outputs ? segment output : 64 outputs ? ram capacity : 8 x 64 = 512 bits ? serial transfer clock frequency (f sck ) : 500 khz max. ? multichip configuration available ? blanking available ? built-in rc oscillation circuit ? package: 100-pin plastic qfp (qfp100-p-1420-0.65-bk) (product name: MSC5301B-02GS-BK) ? semiconductor msc5301b-02 lcd common/segment driver with ram e2b0018-27-y2 this version: may 2000 previous version: nov. 1997
msc5301b-02 ? semiconductor 2/15 8-dot com drv (4-level drv) 64-dot seg drv (4-level drv) 3-8 decoder 64-bit latch 3-bit latch read (3-bit) address counter timing generator 64-bit shift register 64-bit latch chip ctl 6-bit latch 8-bit shift register fram in/out blk ctl por ctl osc input ctl v 4 v 1 c0 c7 v dsp s63 s0 v 2 v 3 v dsp gnd v cc gnd os1 os2 f blk por fram v cc gnd ram ra 2 ra 1 ra 0 wa 2 wa 1 wa 0 we f 64 x 8 = 512 bits latch a / d si sck cs0 cs1 block diagram
msc5301b-02 ? semiconductor 3/15 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 s53 s54 s55 s56 s57 s58 s59 s60 s61 s62 s63 nc c0 nc c1 nc c2 nc c3 nc c4 nc c5 nc c6 nc c7 v 4 v 1 cs0 cs1 latch a/ d si sck por blk frm os1 os2 f v cc gnd v dsp v 2 v 3 s0 s1 s2 s3 s33 s32 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s52 s51 s50 s49 s48 s47 s46 s45 nc s44 s43 s42 s41 s40 s39 s38 s37 s36 s35 s34 nc: no connection 100-pin plastic qfp
msc5301b-02 ? semiconductor 4/15 absolute maximum ratings recommended operating conditions *1 v dsp >v 1 >v 2 3 v 3 >v 4 >gnd parameter condition power supply voltage *1 symbol rating unit ta = 25 c v cc C0.3 to +6.5 v power supply voltage ta = 25 c v dsp C0.3 to +18.0 v input voltage ta = 25 c v in C0.3v v in v cc +0.3 v input voltage ta = 25 c v indp C0.3 v indp v dsp +0.3 v power dissipation ta = 85 c p d 275 mw storage temperature t stg C55 to +125 c parameter condition power supply voltage *1 symbol range unit gnd = 0v v cc 4.5 to 5.5 v power supply voltage gnd = 0v v dsp 6.0 to 16.0 v operating temperature t op C40 to +85 c shift frequency f sck 25 to 500 khz oscillation frequency f f 1.92 to 8.0 khz frame frequency f fr 60 to 250 hz *1 v dsp >v 1 >v 2 3 v 3 >v 4 >gnd
msc5301b-02 ? semiconductor 5/15 electrical characteristics dc characteristics *1 applicable to all input pins *2 applicable to latch, a/ d , si, sck , blk and por pins *3 applicable to cs0, cs1, os1 and fram pins *4 applicable to fram and f pins *5 applicable to c0 - c7 pins *6 applicable to s0 - s63 pins *7 f f = 3.2 khz, f sck = 200 khz, no load, display pattern = checkers v dsp = 16v, current flows into v cc pin. *8 f f = 3.2 khz, f sck = 200 khz, no load, display pattern = checkers v dsp = 16v, current flows into v dsp pin. *9 applicable to os1 pin (v cc = 5v, ta = C40 to +85 c) parameter symbol condition min. typ. max. unit v ih 3.5 v cc v "h" input voltage *1 v il 0 1.5 v "l" input voltage *1 v hs1 0.3 0.8 1.4 v hysteresis voltage 1 *2 v hs2 0.2 0.4 0.8 v hysteresis voltage 2 *9 r pu 10 35 60 k w pull-up resistance *2 v ph 4.9 v pull-up voltage *2 i ih 10 m a "h" input current *3 i il 10 m a "l" input current *3 v oh 4.6 v "h" output voltage *4 v ol 0.4 v "l" output voltage *4 v dp v dsp C0.4 v common driver output voltage v 1 v 1 C0.4 v 1 +0.4 v v 4 v 4 C0.4 v 4 +0.4 v v ss 0.4 v v dp v dsp C0.4 v segment driver output voltage v 2 v 2 C0.4 v 2 +0.4 v v 3 v 3 C0.4 v 3 +0.4 v v ss 0.4 v i cc 6.0 ma supply current 1 i dsp 0.5 ma supply current 2 *7 *8 v i = 0v i in < 1 m a v cc = 5.5v, v ih = 5.5v v cc = 5.5v, v il = 0v i o = C0.4ma i o = 1.6ma v dsp = 10v *5 v dsp = 10v *6 v cc = 5.0v v cc = 5.0v i = C10 m a i = C10 m a i = 10 m a i = 10 m a i = 10 m a i = 10 m a i = +10 m a i = +10 m a
msc5301b-02 ? semiconductor 6/15 sck si latch t 2 t 4 t 1 t 5 t 7 t 8 t 6 a/ d t 3 ac characteristics (v cc = 5v, ta = C40 to +85 c) parameter condition sck clock period symbol min. t 1 2 si data setup time t 2 si data hold time t 3 sck-latch time t 4 latch pulse width t 5 a/ d setup time t 6 typ. max. unit m s 1 m s 1 m s 1 m s 15 m s 1 m s a/ d hold time t 7 1 m s a/ d -sck time t 8 1 m s por, blk fall time t 9 20 m s f , fram rise time t 10 c l = 50 pf 0.3 m s f , fram fall time t 11 c l = 50 pf 0.3 m s frame frequency f fr *1 85 100 115 hz *1 the dispersion for external resistors and capacitors is not included. r s = 1k w , r t = 15k w , c t = 0.01 m f, v cc = 4.5v to 5.5v
msc5301b-02 ? semiconductor 7/15 v cc por, blk 90% 10% gnd v dsp f , fram 90% 10% t 9 t 11 t 10 gnd v 1 v 4 gnd frame a frame b 1/f fr c0 v cc 1/f fr
msc5301b-02 ? semiconductor 8/15 functional description pin functional description ? os1 (pin 39), os2 (pin 40), f (pin 41) these are pins for the rc oscillation circuit. connect external resistors and a capacitor as shown below. when inputting the external clock pulse, input it to os1 pin. os2 and f pins should be left open. cs0 l h l h cs1 l l h h operation mode master mode slave mode slave mode slave mode h : v cc level l : gnd level the relation of frame frequency f fr and internal clock frequency f f is shown by the following equation. (rc oscillation frequency = internal clock frequency) f f = 4 x 8 x f fr in addition, the relation of frame frequency f fr and frame synchronizing signal frequency f fram is shown by the following equation. f fram = f fr /2 ? cs0 (pin 30), cs1 (pin 31) chip select input pins. master and slave modes are determined by cs0 and cs1 as shown in the table below. a maximum of 4 devices can be connected in this manner. use the master mode when using a single chip. os 1 os 2 f c t r s r t
msc5301b-02 ? semiconductor 9/15 ? fram (pin 38) this is an input and output pin for the frame synchronizing signal to be used for master/slave configuration. it becomes an output pin in master mode and an input pin in slave mode. ? si (pin 34) this is a serial data input pin of address data (8 bits) and segment data (64 bits). a pull-up resistor (10 k w - 60 k w ) and the schmitt circuit are contained. the serial data is shifted at the rising edge of sck . ? sck (pin 35) this is a shift clock input pin of address data (8 bits) and segment data (64 bits). the serial data is shifted at the rising edge of sck pulse. a pull-up resistor (10 k w - 60 k w ) and the schmitt circuit are contained. ? latch (pin 32) this is a latch pulse input pin of address data (8 bits) and segment data (64 bits). the latch data comes through at "h" level of latch and the data just before "h" level is latched at "l" level. a pull-up resistor (10 k w - 60 k w ) and the schmitt circuit are contained. ?a/ d (pin 33) this is a data select signal input pin of address data (8 bits) and segment data (64 bits). "h" level is set in the case of address 8-bit input and "l" level is set in the case of segment data 64-bit input. a pull-up resistor (10 k w - 60 k w ) and the schmitt circuit are contained. ?v dsp (pin 44), v 1 (pin 29), v 2 (pin 45), v 3 (pin 46), v 4 (pin 28), v cc (pin 42), gnd (pin 43) these are power supply pins for this lsi and bias power supply pins for lcd driving. v cc , which is a power supply pin, is from 4.5v to 5.5v; gnd, which is a ground pin, is 0v; v dsp , which is an lcd driving power supply pin, is usually used in the range between 6v and 16v. v 1 , v 2 , v 3 and v 4 are bias power supply pins for lcd driving and are usually used by supplying bias voltage from an external source.
msc5301b-02 ? semiconductor 10/15 ? blk (pin 37) this is an input pin to control the lcd panel display. when a "h" level is input (or when this pin is open), the segment output pins s0 - s63 come to the levels v 2 - v 3 and the lcd panel is turned off. in addition, during this period, the data read from a display ram is stopped but writing into the display ram of address and segment data inputted from the si pin is available. when this pin is changed from "h" level to "l", the frame synchronizing signal fram is output within the 2 cycles of an internal clock f f , and it is synchronized at multi-chip. then, the display ram address is set to "000". after 1/8 frame cycle from fram signal generation, the output is applied from the "001" data of the display ram address to the segment driver. because the display ram contents are undefined at the time the power is turned on, keep this pin to "h" level (or leave open) until writing data to the ram is completed. a pull-up resistor (10k w - 60k w ) and the schmitt circuit are contained. ? por (pin 36) this is a power-on-reset input pin. when a "h" level is input (or when this pin is open), the common and segment outputs come to the static light-out state in no relation to the blk pin and the segment output pins s0 - s63 become v 3 level and the common output pins c0 - c8 become v 4 level. when this pin is changed from "h" level to "l", the frame synchronizing signal fram is output within the 2 cycles of an interval clock f f , and it is synchronized when multiple devices are connected and is moreover dynamic-operated from the frame b . then, the display ram address is set to "000". after 1/8 frame cycle from fram signal generation, the "001" data of the display ram address is output to the segment driver. however, because the blk pin is usually at "h" level when the power-on-reset is released, reading data from the display ram is stopped and light-out segment data is forcibly transferred to the segment output. a pull-up resistor (10k w - 60k w ) and the schmitt circuit are contained. ? c0 (pin 13) - c7 (pin 27) these are 8-output pins of the common driver which are used for lcd panel driving. the outputs of 4 levels are obtained (v dsp and gnd are select levels, and v 1 and v 4 are nonselect levels). ? s0 (pin 47) - s63 (pin 11) these are 64-output pins of segment driver which are used for lcd panel driving. the outputs of 4 levels are obtained (v dsp and gnd are select levels, which correspond to "1" of the display ram data, and v 2 and v 3 are nonselect levels, which correspond to "0" of the display ram data). notes on use note the following when turning power on and off: the lcd drivers of this ic require a high voltage. for this reason, if a high voltage is applied to the lcd drivers with the logic power supply floating, excess current flows. this may damage the ic. be sure to carry out the following power-on and power-off sequences: when turning power on: first v cc on, next v dsp , v 4 , v 3 , v 2 , v 1 on. or both on at the same time. when turning power off: first v dsp , v 4 , v 3 , v 2 , v 1 off, next v cc off. or both off at the same time.
msc5301b-02 ? semiconductor 11/15 a2 0 0 0 0 1 1 1 1 a1 0 0 1 1 0 0 1 1 a0 0 1 0 1 0 1 0 1 s63 s0 c0 c1 c2 c3 c4 c5 c6 c7 1/8 duty address data number of dots in x direction (64) relation between lcd screen size and display ram this lcd driver has a built-in ram for the display of 8 64 = 512 bits and the address corresponds to the duty of the lcd. the data corresponds to the number of dots in the x direction. the relation between the lcd screen size and the display ram is shown below. relation between frame cycle and display ram data the output of the display ram data corresponds to the segment output. the relation between the frame cycle and the display ram data is as follows: segment output (contents of ram) 1 frame cycle 000 001 010 011 110 111 000 001 first line address
msc5301b-02 ? semiconductor 12/15 multiple configuration this lcd driver can form multiple configuration. it is possible to form a maximum of 4 devices (a panel of up to 256 8 dots in size can be formed) by using chip select signals cs0 and cs1. the devices in multiple configuration must be synchronized with one another. in this configuration, one device in the master mode, where the original oscillation signal f and the synchronous signal fram are output, and the other devices in the slave mode, where the original oscillation signal f and the synchronous signal fram are input, are used in combination. refer to items cs0 and cs1 of the pin description on the mode setting method. the original oscillation signal output pin f of the master mode devices is connected to the os1 pin of the slave mode device and the synchronizing signal pin fram is also connected to the fram pin of the slave mode device. connect si, sck , latch, a/ d , por and blk of the master mode devices to si, sck , latch, a/ d , por and blk of each of the slave mode devices and connect them to cpu for control. in addition, connect the devices so that v dsp , v 1 , v 2 , v 3 , v 4 and gnd are shared between the devices, and connect them to each voltage level divided by resistors. address data configuration the lower address, which is the address of the display ram, corresponds to the common sides c0 - c7 of lcd panel. dummy data 1 must be always set to "h". the upper address corresponds to the logical state of chip select pins cs0 and cs1 and lower address is set to the chip only with which corresponded. for the chip to output the common signal ( f , fram), set both of the upper address 2 bits to "l". the 2 bits of dummy data can be set to either "l" or "h". 7654 3210 dummy data 2 upper address lower address 2 bits 2 bits (msb) (lsb) 3 bits 1 bit dummy data 1 dm2 dm1 cs1 cs0 a2 a1 a0 dm0
msc5301b-02 ? semiconductor 13/15 serial signal to be input from cpu the following signals are input from an external cpu to this lcd driver: - serial transfer clock ? sck - serial transfer data ? si - serial transfer latch ? latch - serial data select ? a/ d the operations are shown in the following table. timing for serial signal transferred from cpu notes: 1. be sure to set the address before writing the segment data to ram. then, write the segment data to ram. 2. while the por pin is "h" (upon power-on reset), neither address data nor segment data can be entered. 12345678 12 3 6364 a/ d "h" at address data setting "l" at segment data setting sck si latch a0 a1 a2 cs0 cs1 dummy dummy s 63 s 62 s 61 s 1 s 0 address data (8 bits) segment data (64 bits) msb lsb address latch signal ram write signal dummy (always "h") mode latch si address data input mode h l segment data input mode shifts at the rising edge shifts at the rising edge 8-bit address data is latched at falling edge (level type) 64-bit segment data is latched at falling edge (level type) 8-bit address data serial input from lsb side 64-bit segment data the first segment data shifted into the shift register corresponds to s63. "1" : light-on data, "0" : light-out data sck a/ d
msc5301b-02 ? semiconductor 14/15 dynamic operation (normal operation) dynamic light-out state frame b frame b frame a frame a frame b frame b frame a ram address 0 - 7 frame a 0 - 7 0 - 0 1 - 7 0 - 7 0 - 7 0 - 7 segment signal output common signal output fram f (external r and c) blk por v cc operation upon power on (when single device used)
msc5301b-02 ? semiconductor 15/15 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp100-p-1420-0.65-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.29 typ. mirror finish
msc5301b-02 ? semiconductor 16/15 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 2000 oki electric industry co., ltd. printed in japan

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